@inproceedings{7cbfb1aa9470415d8f1fd455c39e24cc,
title = "Yield and layout issues in fault tolerant VLSI architectures",
abstract = "Yield and layout are two important but often ignored issues in the design of fault tolerant VLSI systems. The authors present a framework for the systematic analysis of yield and area-efficient layout of fault-tolerant architectures. A multiple level redundancy tree is considered as a target architecture to demonstrate their analysis technique.",
author = "Upadhyaya, \{S. J.\} and Chen, \{Yung Yuan\}",
note = "Publisher Copyright: {\textcopyright} 1991 IEEE.; 4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991 ; Conference date: 04-01-1991 Through 08-01-1991",
year = "1991",
doi = "10.1109/ISVD.1991.185126",
language = "English",
series = "Proceedings of the IEEE International Conference on VLSI Design",
publisher = "IEEE Computer Society",
pages = "255--260",
booktitle = "VLSI Design 1991 - Digest of Papers - 4th CSI/IEEE International Symposium on VLSI Design",
address = "United States",
}