Widening avoidance in matched and mismatched filter outputs via factored representation with chip compounding

In some digital radar systems, the matched filter is followed by a mismatched filter. In order to achieve computational efficiency, both the matched and mismatched filters could be implemented as several cascaded stages. This is particularly the case when the radar code is compounded from two codes or more. This is also the case when mismatched filters, such as those using sidelobe inversion, are designed as a cascade of several stages. If these filters are implemented with the highly sampled chip included in every stage, then each stage would contribute additional mainlobe widening. The contribution of this work is to isolate the effect of the highly sampled chip by observing that it could be represented in a separate stage following a purely digital implementation of the matched and the mismatched filter stages. In essence the effect of the chip is viewed as compounding of the digital code. As a result, computational efficiency and sidelobe reduction are achieved with only one widening effect due to the chip matched filter, regardless of the number of matched and mismatched filter stages. Using high sampling frequency, the received signal can be processed very accurately making the system suitable for digital radar systems with or without the use of an intermediate frequency. Isolating the chip in its own matched filter allows for replacing it with a different waveform that can lead to additional advantages. We call this subchip encoding and some examples are presented.