TY - GEN
T1 - VLSI neural network architectures
AU - Sridhar, R.
AU - Shin, Yong Chul
N1 - Publisher Copyright:
© 1993 IEEE.
PY - 1993
Y1 - 1993
N2 - VLSI architectures for neural networks are presented. Neural networks have wide-ranging applications in classification, control, and optimization. With the need for real-time performance, VLSI neural networks have gained significant attention. Digital, analog, and mixed-mode designs are used for this application. Modular and reconfigurable designs are necessary so that various neural network models can be easily configured.
AB - VLSI architectures for neural networks are presented. Neural networks have wide-ranging applications in classification, control, and optimization. With the need for real-time performance, VLSI neural networks have gained significant attention. Digital, analog, and mixed-mode designs are used for this application. Modular and reconfigurable designs are necessary so that various neural network models can be easily configured.
UR - https://www.scopus.com/pages/publications/84889963826
U2 - 10.1109/ASIC.1993.410845
DO - 10.1109/ASIC.1993.410845
M3 - Conference contribution
AN - SCOPUS:84889963826
T3 - Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
SP - 560
EP - 569
BT - Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
Y2 - 27 September 1993 through 1 October 1993
ER -