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VerilogA based compact model of a three-terminal ME-MTJ device

  • University of Texas at Dallas

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

We present the first set of VerilogA based models for Magneto-Electric Magnetic Tunnel Junction (ME-MTJ) devices. The compact models have been developed in Verilog-A language and validated by electrical simulations using Cadence Spectre and Schematic Editor. We show simulation results of the ME-MTJ based logic functions i.e. Buffer/Inverter and Majority gate and also show their integrated memory capability. In addition, we have validated the methodology with a full adder simulation. Experimental parameters are included in the models to enhance simulation accuracy. The simulation results indicate that the ME-MTJ models can be used extensively for more complex circuit design.

Original languageEnglish
Title of host publication16th International Conference on Nanotechnology - IEEE NANO 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages145-148
Number of pages4
ISBN (Electronic)9781509039142
DOIs
StatePublished - Nov 21 2016
Event16th IEEE International Conference on Nanotechnology - IEEE NANO 2016 - Sendai, Japan
Duration: Aug 22 2016Aug 25 2016

Publication series

Name16th International Conference on Nanotechnology - IEEE NANO 2016

Conference

Conference16th IEEE International Conference on Nanotechnology - IEEE NANO 2016
Country/TerritoryJapan
CitySendai
Period08/22/1608/25/16

Keywords

  • Adder
  • Logic
  • Magnetic Tunnel Junction (MTJ)
  • Magneto-Electric Magnetic Tunnel Junction (ME-MTJ)
  • Memory
  • Spintronics
  • VerilogA

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