Variation aware low power buffered interconnect design

Ashok Narasimhan; Ramalingam Sridhar

doi:10.1109/SOCCON.2009.5398020

Variation aware low power buffered interconnect design

Ashok Narasimhan
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Enhancing interconnect robustness against variations is crucial to system performance and reliability in sub-65nm technologies. We present a new interconnect design methodology to optimize power consumption and robustness during buffer insertion. Using closed form expressions for interconnect delay and delay variation, we construct a design space for the interconnect. Through power-robustness tradeoff analysis of the design space, the buffering solution that minimizes power consumption while satisfying the delay and robustness constraints is computed. Comparisons with spice simulations show the effectiveness of this technique.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2009
Pages	365-368
Number of pages	4
DOIs	https://doi.org/10.1109/SOCCON.2009.5398020
State	Published - 2009
Event	IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland Duration: Sep 9 2009 → Sep 11 2009

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2009

Conference

Conference	IEEE International SOC Conference, SOCC 2009
Country/Territory	Ireland
City	Belfast
Period	09/9/09 → 09/11/09

Keywords

Delay variation
Interconnect delay
Low power
Optimal buffer insertion
Variability

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10.1109/SOCCON.2009.5398020

Cite this

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title = "Variation aware low power buffered interconnect design",

abstract = "Enhancing interconnect robustness against variations is crucial to system performance and reliability in sub-65nm technologies. We present a new interconnect design methodology to optimize power consumption and robustness during buffer insertion. Using closed form expressions for interconnect delay and delay variation, we construct a design space for the interconnect. Through power-robustness tradeoff analysis of the design space, the buffering solution that minimizes power consumption while satisfying the delay and robustness constraints is computed. Comparisons with spice simulations show the effectiveness of this technique.",

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AU - Sridhar, Ramalingam

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N2 - Enhancing interconnect robustness against variations is crucial to system performance and reliability in sub-65nm technologies. We present a new interconnect design methodology to optimize power consumption and robustness during buffer insertion. Using closed form expressions for interconnect delay and delay variation, we construct a design space for the interconnect. Through power-robustness tradeoff analysis of the design space, the buffering solution that minimizes power consumption while satisfying the delay and robustness constraints is computed. Comparisons with spice simulations show the effectiveness of this technique.

AB - Enhancing interconnect robustness against variations is crucial to system performance and reliability in sub-65nm technologies. We present a new interconnect design methodology to optimize power consumption and robustness during buffer insertion. Using closed form expressions for interconnect delay and delay variation, we construct a design space for the interconnect. Through power-robustness tradeoff analysis of the design space, the buffering solution that minimizes power consumption while satisfying the delay and robustness constraints is computed. Comparisons with spice simulations show the effectiveness of this technique.

KW - Delay variation

KW - Interconnect delay

KW - Low power

KW - Optimal buffer insertion

KW - Variability

UR - https://www.scopus.com/pages/publications/77949592789

U2 - 10.1109/SOCCON.2009.5398020

DO - 10.1109/SOCCON.2009.5398020

M3 - Conference contribution

AN - SCOPUS:77949592789

SN - 9781424452200

T3 - Proceedings - IEEE International SOC Conference, SOCC 2009

SP - 365

EP - 368

BT - Proceedings - IEEE International SOC Conference, SOCC 2009

T2 - IEEE International SOC Conference, SOCC 2009

Y2 - 9 September 2009 through 11 September 2009

ER -

Variation aware low power buffered interconnect design

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Keywords

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