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Use of performance path test to optimize yield

  • IBM

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Performance path test provides an innovative alternative to PSRO performance screens and functional pattern test for manufacturing performance screening. The process window sigma associated with a desired screen point is used in a special timing run to create the expected delay for paths in the product. These expected delays are used to screen products. Products passing this test will meet requirements in client applications. Parts that fail will not meet product design assumptions and are not shipped. Performance path test avoids yield loss, false accept, and false reject problems associated with use of edge PSRO monitors.

Original languageEnglish
Title of host publication2013 24th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2013
Pages206-211
Number of pages6
DOIs
StatePublished - 2013
Event2013 24th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2013 - Saratoga Springs, NY, United States
Duration: May 14 2013May 16 2013

Publication series

NameASMC (Advanced Semiconductor Manufacturing Conference) Proceedings
ISSN (Print)1078-8743

Conference

Conference2013 24th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2013
Country/TerritoryUnited States
CitySaratoga Springs, NY
Period05/14/1305/16/13

Keywords

  • Fmax
  • performance
  • timing
  • yield optimization

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