Unified approach to designing fault-tolerant processor ensembles

Processor ensembles (PEN) form part of parallel processing systems. A unified approach to designing fault-tolerant PENs is presented. The approach is illustrated by presenting fault-tolerant schemes for several commonly used interconnection topologies. The fault-tolerance scheme is shown to be 'area-efficient'. Unlike other fault-tolerance analyses of fault-tolerant PENs that have appeared in the literature, the authors' reliability analysis takes into account switch failures along with processor and link failures.