Toward an analog VLSI implementation of a decision making model

Yili Quan; Albert H. Titus

doi:10.1109/IJCNN.2005.1555907

Toward an analog VLSI implementation of a decision making model

Yili Quan
, Albert H. Titus

Department of Biomedical Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes an analog circuit implementation of on-chip learning for the Lens Model by using Adaptive Linear Neuron networks (ADALINE). The on-chip learning circuit has been designed using MOS transistors operating in the subthreshold regime. The proposed circuit has been developed and simulated using the CMOS 1.5μm AMI ABN process. The parameters of the correlation coefficient equation are current signals that can be controlled through the voltages to produce the square root behavior. The circuit is biased at 1.5V to lower the power dissipation. Spice simulations are included to illustrate the circuit performance.

Original language	English
Title of host publication	Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005
Pages	645-650
Number of pages	6
DOIs	https://doi.org/10.1109/IJCNN.2005.1555907
State	Published - 2005
Event	International Joint Conference on Neural Networks, IJCNN 2005 - Montreal, QC, Canada Duration: Jul 31 2005 → Aug 4 2005

Publication series

Name	Proceedings of the International Joint Conference on Neural Networks
Volume	1

Conference

Conference	International Joint Conference on Neural Networks, IJCNN 2005
Country/Territory	Canada
City	Montreal, QC
Period	07/31/05 → 08/4/05

Access to Document

10.1109/IJCNN.2005.1555907

Cite this

@inproceedings{bb87d90f6b9a41b7ba588b0c1abdad4e,

title = "Toward an analog VLSI implementation of a decision making model",

abstract = "This paper describes an analog circuit implementation of on-chip learning for the Lens Model by using Adaptive Linear Neuron networks (ADALINE). The on-chip learning circuit has been designed using MOS transistors operating in the subthreshold regime. The proposed circuit has been developed and simulated using the CMOS 1.5μm AMI ABN process. The parameters of the correlation coefficient equation are current signals that can be controlled through the voltages to produce the square root behavior. The circuit is biased at 1.5V to lower the power dissipation. Spice simulations are included to illustrate the circuit performance.",

author = "Yili Quan and Titus, \{Albert H.\}",

year = "2005",

doi = "10.1109/IJCNN.2005.1555907",

language = "English",

isbn = "0780390482",

series = "Proceedings of the International Joint Conference on Neural Networks",

pages = "645--650",

booktitle = "Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005",

note = "International Joint Conference on Neural Networks, IJCNN 2005 ; Conference date: 31-07-2005 Through 04-08-2005",

}

Quan, Y & Titus, AH 2005, Toward an analog VLSI implementation of a decision making model. in Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005., 1555907, Proceedings of the International Joint Conference on Neural Networks, vol. 1, pp. 645-650, International Joint Conference on Neural Networks, IJCNN 2005, Montreal, QC, Canada, 07/31/05. https://doi.org/10.1109/IJCNN.2005.1555907

Toward an analog VLSI implementation of a decision making model. / Quan, Yili; Titus, Albert H.
Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005. 2005. p. 645-650 1555907 (Proceedings of the International Joint Conference on Neural Networks; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Titus, Albert H.

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N2 - This paper describes an analog circuit implementation of on-chip learning for the Lens Model by using Adaptive Linear Neuron networks (ADALINE). The on-chip learning circuit has been designed using MOS transistors operating in the subthreshold regime. The proposed circuit has been developed and simulated using the CMOS 1.5μm AMI ABN process. The parameters of the correlation coefficient equation are current signals that can be controlled through the voltages to produce the square root behavior. The circuit is biased at 1.5V to lower the power dissipation. Spice simulations are included to illustrate the circuit performance.

AB - This paper describes an analog circuit implementation of on-chip learning for the Lens Model by using Adaptive Linear Neuron networks (ADALINE). The on-chip learning circuit has been designed using MOS transistors operating in the subthreshold regime. The proposed circuit has been developed and simulated using the CMOS 1.5μm AMI ABN process. The parameters of the correlation coefficient equation are current signals that can be controlled through the voltages to produce the square root behavior. The circuit is biased at 1.5V to lower the power dissipation. Spice simulations are included to illustrate the circuit performance.

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DO - 10.1109/IJCNN.2005.1555907

M3 - Conference contribution

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T3 - Proceedings of the International Joint Conference on Neural Networks

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Y2 - 31 July 2005 through 4 August 2005

ER -

Toward an analog VLSI implementation of a decision making model

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