Abstract
The finite element procedure with the unified disturbed state modeling concept presented in Part I, Basaran et al. (1998), is verified here with respect to laboratory test results for Pb40/Sn60 eutectic solder alloy. This solder alloy is a commonly used interconnection material for surface mount technology packages. It is demonstrated that the proposed procedure provides highly satisfactory correlation with the observed laboratory behavior of materials and with test results for a chip-substrate system simulated in the laboratory.
| Original language | English |
|---|---|
| Pages (from-to) | 48-53 |
| Number of pages | 6 |
| Journal | Journal of Electronic Packaging |
| Volume | 120 |
| Issue number | 1 |
| DOIs | |
| State | Published - Mar 1998 |
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