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Thermal Stress Analysis of Multi-layered Microelectronic Packaging

  • SUNY Buffalo
  • Intel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An accurate estimate of thermal stresses in multilayered microelectronics structures along the bonded interfaces is crucial for design and prediction of delamination-related failures. Compared with numerical method, analytical solution can offer a more rapid method to obtain the stresses at the interface. An analytical model for ply-level sub-laminate analysis is investigated in this paper. The presented theory treats each layer as a beam-type plate with appropriate interface and surface conditions. As an example, the results are shown for the three-layer beam problem with special orthotropic material properties. Analytical model results are compared with the finite element analyis results.

Original languageEnglish
Title of host publicationAdvances in Electronic Packaging; Electrical Design, Simulation, and Test, Mems, Materials and Processing, Modeling and Characterization
Pages449-460
Number of pages12
StatePublished - 2001
EventPacific Rim/International, Intersociety Electronic Packaging Technical/Business Conference and Exhibition - Kauai, Hi, United States
Duration: Jul 8 2001Jul 13 2001

Publication series

NameAdvances in Electronic Packaging
Volume1

Conference

ConferencePacific Rim/International, Intersociety Electronic Packaging Technical/Business Conference and Exhibition
Country/TerritoryUnited States
CityKauai, Hi
Period07/8/0107/13/01

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