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The interlaced carry-arrest adder

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The interlaced carry-arrest adder (ICA) is introduced as a new, fast multioperand adder to compute the sum of four or more numbers. To avoid the need to propagate the carry all the way to the most significant bits, periodic gaps of zeros are created in each of the summands by moving certain pattern of their bits into auxiliary arrays. The pattern of the moved bits is staggered, such that the auxiliary arrays are filled without overlaps and with a periodic pattern of gaps left unfilled such that the resulting auxiliary numbers also have the same staggered zero patterns as the summands. These gaps convert a sum of numbers with arbitrarily large number of bits to independent parallel additions of short pairs of numbers. This is so since any carry bits resulting from the addition of pairs of short numbers are trapped in the gaps. This allows for fast parallel addition that is truly independent of the number of bits of the summands, and depend only on the number of bits in the short numbers added in parallel, and logarithmically on the number of numbers to be added.

Original languageEnglish
Title of host publication2010 International Conference on Microelectronics, ICM'10
Pages120-123
Number of pages4
DOIs
StatePublished - 2010
Event2010 International Conference on Microelectronics, ICM'10 - Cairo, Egypt
Duration: Dec 19 2010Dec 22 2010

Publication series

NameProceedings of the International Conference on Microelectronics, ICM

Conference

Conference2010 International Conference on Microelectronics, ICM'10
Country/TerritoryEgypt
CityCairo
Period12/19/1012/22/10

Keywords

  • Multioperand interlaced carry-arrest adder
  • Multiplication
  • Parallel computing
  • Partial sums
  • Sums

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