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Test scheduling for system-on-a-chip using test resource grouping

  • Kwandong University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Test scheduling has been known to be one of the efficient techniques for reducing testing time of Ss'stem-on-a-Chip(SoC). In this paper, a heuristic algorithm, in which test resources are grouped and arranged based on the size of product of power dissipation and test time of each core together with total power consumption in core-based SoC is proposed. We select test resource groups which have maximum power consumption but do not exceed the constrained power consumption and make the testing time slot of resources aligned at the initial position to minimize the idling test time of test resources.

Original languageEnglish
Title of host publicationASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
EditorsTing-Ao Tang, Wenhong Li, Huihua Yu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1167-1170
Number of pages4
ISBN (Electronic)078037889X
DOIs
StatePublished - 2003
Event5th International Conference on ASIC, ASICON 2003 - Beijing, China
Duration: Oct 21 2003Oct 24 2003

Publication series

NameIEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
Volume2
ISSN (Print)1523-553X

Conference

Conference5th International Conference on ASIC, ASICON 2003
Country/TerritoryChina
CityBeijing
Period10/21/0310/24/03

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