Techniques of power-gating to kill sub-threshold leakage

Changbo Long; Jinjun Xiong; Yongpan Liu

doi:10.1109/APCCAS.2006.342219

Techniques of power-gating to kill sub-threshold leakage

Changbo Long
, Jinjun Xiong
, Yongpan Liu

Department of Computer Science and Engineering

University of California at Los Angeles
Tsinghua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Sub-threshold leakage has increased dramatically with technology scaling, and it already consumes a significant portion of the total power budget in current high-end chip designs. This paper presents a state-of-the-art overview of the power gating techniques that promise to reduce sub-threshold leakage power by up to three orders of magnitude. By emphasizing the challenges and up-to-date solutions, this paper provides an in-depth vision of the current status of power-gating techniques. By analyzing the historic development of power-gating, this paper also outlines possible future evolution courses of the technique.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	952-955
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342219
State	Published - 2006
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: Dec 4 2006 → Dec 6 2006

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	12/4/06 → 12/6/06

Access to Document

10.1109/APCCAS.2006.342219

Cite this

@inproceedings{0f7939ca2baf46ef824f9fb8aabf1b00,

title = "Techniques of power-gating to kill sub-threshold leakage",

abstract = "Sub-threshold leakage has increased dramatically with technology scaling, and it already consumes a significant portion of the total power budget in current high-end chip designs. This paper presents a state-of-the-art overview of the power gating techniques that promise to reduce sub-threshold leakage power by up to three orders of magnitude. By emphasizing the challenges and up-to-date solutions, this paper provides an in-depth vision of the current status of power-gating techniques. By analyzing the historic development of power-gating, this paper also outlines possible future evolution courses of the technique.",

author = "Changbo Long and Jinjun Xiong and Yongpan Liu",

year = "2006",

doi = "10.1109/APCCAS.2006.342219",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "952--955",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

}

Long, C, Xiong, J & Liu, Y 2006, Techniques of power-gating to kill sub-threshold leakage. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145552, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 952-955, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 12/4/06. https://doi.org/10.1109/APCCAS.2006.342219

Techniques of power-gating to kill sub-threshold leakage. / Long, Changbo; Xiong, Jinjun; Liu, Yongpan.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 952-955 4145552 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Techniques of power-gating to kill sub-threshold leakage

AU - Long, Changbo

AU - Xiong, Jinjun

AU - Liu, Yongpan

PY - 2006

Y1 - 2006

N2 - Sub-threshold leakage has increased dramatically with technology scaling, and it already consumes a significant portion of the total power budget in current high-end chip designs. This paper presents a state-of-the-art overview of the power gating techniques that promise to reduce sub-threshold leakage power by up to three orders of magnitude. By emphasizing the challenges and up-to-date solutions, this paper provides an in-depth vision of the current status of power-gating techniques. By analyzing the historic development of power-gating, this paper also outlines possible future evolution courses of the technique.

AB - Sub-threshold leakage has increased dramatically with technology scaling, and it already consumes a significant portion of the total power budget in current high-end chip designs. This paper presents a state-of-the-art overview of the power gating techniques that promise to reduce sub-threshold leakage power by up to three orders of magnitude. By emphasizing the challenges and up-to-date solutions, this paper provides an in-depth vision of the current status of power-gating techniques. By analyzing the historic development of power-gating, this paper also outlines possible future evolution courses of the technique.

UR - https://www.scopus.com/pages/publications/50249156900

U2 - 10.1109/APCCAS.2006.342219

DO - 10.1109/APCCAS.2006.342219

M3 - Conference contribution

AN - SCOPUS:50249156900

SN - 1424403871

SN - 9781424403875

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 952

EP - 955

BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Techniques of power-gating to kill sub-threshold leakage

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this