System-on-chip testability using LSSD scan structures

Kamran Zarrineh; Shambhu J. Upadhyaya; Vivek Chickermane

doi:10.1109/54.922805

System-on-chip testability using LSSD scan structures

Kamran Zarrineh
, Shambhu J. Upadhyaya
, Vivek Chickermane

Department of Computer Science and Engineering

Sun Microsystems
Global Foundries, Inc.

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

A technology-independent test synthesis tool that extends the basic level-sensitive scan design (LSSD) boundary scan methodology is presented. The tool reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.

Original language	English
Pages (from-to)	83-97
Number of pages	15
Journal	IEEE Design and Test of Computers
Volume	18
Issue number	3
DOIs	https://doi.org/10.1109/54.922805
State	Published - May 2001

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@article{7d5a2b5541664a419a5168982b1bcda3,

title = "System-on-chip testability using LSSD scan structures",

abstract = "A technology-independent test synthesis tool that extends the basic level-sensitive scan design (LSSD) boundary scan methodology is presented. The tool reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.",

author = "Kamran Zarrineh and Upadhyaya, \{Shambhu J.\} and Vivek Chickermane",

year = "2001",

month = may,

doi = "10.1109/54.922805",

language = "English",

volume = "18",

pages = "83--97",

journal = "IEEE Design and Test of Computers",

issn = "0740-7475",

number = "3",

}

TY - JOUR

T1 - System-on-chip testability using LSSD scan structures

AU - Zarrineh, Kamran

AU - Upadhyaya, Shambhu J.

AU - Chickermane, Vivek

PY - 2001/5

Y1 - 2001/5

N2 - A technology-independent test synthesis tool that extends the basic level-sensitive scan design (LSSD) boundary scan methodology is presented. The tool reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.

AB - A technology-independent test synthesis tool that extends the basic level-sensitive scan design (LSSD) boundary scan methodology is presented. The tool reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.

UR - https://www.scopus.com/pages/publications/0035336886

U2 - 10.1109/54.922805

DO - 10.1109/54.922805

M3 - Article

AN - SCOPUS:0035336886

SN - 0740-7475

VL - 18

SP - 83

EP - 97

JO - IEEE Design and Test of Computers

JF - IEEE Design and Test of Computers

IS - 3

ER -

System-on-chip testability using LSSD scan structures

Abstract

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