Sub-100 nm integrated ferroelectric tunnel junction devices using hydrogen silsesquioxane planarization

Ferroelectric tunnel junction (FTJ) is an emerging low power and nonvolatile memory device for beyond-complementary metal-oxide-semiconductor (CMOS) applications. The scalability of the FTJ devices need to be investigated for successful integration with CMOS for future nonvolatile circuits. In this article, a novel fabrication methodology is demonstrated to fabricate sub-100 nm FTJs. The fabrication process employs planarization with hydrogen silsesquioxane, an electron beam sensitive resist that is transformed into insulating material after curing. The method uses low temperature processes to minimize degradation of the device structures. The process is implemented to fabricate a Ti/SrTiO₃/BaTiO₃/SrRuO₃ FTJs of size 75 × 75 nm², and the fabricated device shows ferroelectric switching with large ON/OFF ratio (∼125).