Speed and power comparison of CMOS wave pipelined systems and low power WTGL

Ramalingam Sridhar; Alfonso Martinez-Smith; Brian McGee

Speed and power comparison of CMOS wave pipelined systems and low power WTGL

Ramalingam Sridhar
, Alfonso Martinez-Smith
, Brian McGee

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Contribution to journal › Conference article › peer-review

Abstract

CMOS wave pipelining is a technique used in high performance digital system design. This paper compares speed and power performance of various CMOS wave pipelined systems. It also presents a modified wave pipelined transmission gate logic for low-power applications and its associated fine tuning method, resulting in a design style for performance in regard to power, delay, and throughput.

Original language	English
Pages (from-to)	156-159
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - 1996
Event	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: May 12 1996 → May 15 1996

Cite this

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title = "Speed and power comparison of CMOS wave pipelined systems and low power WTGL",

abstract = "CMOS wave pipelining is a technique used in high performance digital system design. This paper compares speed and power performance of various CMOS wave pipelined systems. It also presents a modified wave pipelined transmission gate logic for low-power applications and its associated fine tuning method, resulting in a design style for performance in regard to power, delay, and throughput.",

author = "Ramalingam Sridhar and Alfonso Martinez-Smith and Brian McGee",

year = "1996",

language = "English",

volume = "4",

pages = "156--159",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) ; Conference date: 12-05-1996 Through 15-05-1996",

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TY - JOUR

T1 - Speed and power comparison of CMOS wave pipelined systems and low power WTGL

AU - Sridhar, Ramalingam

AU - Martinez-Smith, Alfonso

AU - McGee, Brian

PY - 1996

Y1 - 1996

N2 - CMOS wave pipelining is a technique used in high performance digital system design. This paper compares speed and power performance of various CMOS wave pipelined systems. It also presents a modified wave pipelined transmission gate logic for low-power applications and its associated fine tuning method, resulting in a design style for performance in regard to power, delay, and throughput.

AB - CMOS wave pipelining is a technique used in high performance digital system design. This paper compares speed and power performance of various CMOS wave pipelined systems. It also presents a modified wave pipelined transmission gate logic for low-power applications and its associated fine tuning method, resulting in a design style for performance in regard to power, delay, and throughput.

UR - https://www.scopus.com/pages/publications/0029705565

M3 - Conference article

AN - SCOPUS:0029705565

SN - 0271-4310

VL - 4

SP - 156

EP - 159

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)

Y2 - 12 May 1996 through 15 May 1996

ER -

Speed and power comparison of CMOS wave pipelined systems and low power WTGL

Abstract

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