Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic variation and random channel length (L_eff) variation of transistors on interconnect design, We first construct a table look-up based interconnect RC parasitic model considering CMP effects with optimized fill insertion. Based on the model, we solve the simultaneous buffer insertion, wire sizing and fill insertion (SBWF) problem under CMP variation, We also extend the SBWF problem to consider the random L_eff variation (vSBWF). We approach the resulting vSBWF problem by (1) incorporating probability density function (PDF) into the SBWF algorithm; and (2) developing an efficient heuristic for PDF pruning, whose practical optimality is verified by an accurate but much slower pruning. Experimental results show that the SBWF design improves timing by 1.0% and reduces power by 5.7% on average with 7.4% less buffer area over the conventional buffer insertion and wire sizing design followed by fill insertion (SBW + Fill), and that the vSBWF design reduces yield loss due to CMP and L_eff variations by 44.3% on average over the SBW + Fill design. The runtime of vSBWF is 8.3x that of SBWF, and vSBWF for the largest example containing 3103 sinks finishes in 1.24 minutes.