RG-SRAM: A low gate leakage memory design

Charan Thondapu; Praveen Elakkumanan; Ramalingam Sridhar

doi:10.1109/ISVLSI.2005.64

RG-SRAM: A low gate leakage memory design

Charan Thondapu
, Praveen Elakkumanan
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel Reduced-Gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in Very Deep Sub-Micron (VDSM) cache and embedded memories.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Editors	A. Smailagic, N. Ranganathan
Pages	295-296
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2005.64
State	Published - 2005
Event	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design - Tampa, FL, United States Duration: May 11 2005 → May 12 2005

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Conference

Conference	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Country/Territory	United States
City	Tampa, FL
Period	05/11/05 → 05/12/05

Access to Document

10.1109/ISVLSI.2005.64

Cite this

Thondapu, C., Elakkumanan, P., & Sridhar, R. (2005). RG-SRAM: A low gate leakage memory design. In A. Smailagic, & N. Ranganathan (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design (pp. 295-296). (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI). https://doi.org/10.1109/ISVLSI.2005.64

@inproceedings{29cea8d9450343e18f5606740c27e832,

title = "RG-SRAM: A low gate leakage memory design",

abstract = "The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel Reduced-Gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in Very Deep Sub-Micron (VDSM) cache and embedded memories.",

author = "Charan Thondapu and Praveen Elakkumanan and Ramalingam Sridhar",

year = "2005",

doi = "10.1109/ISVLSI.2005.64",

language = "English",

isbn = "076952365X",

series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI",

pages = "295--296",

editor = "A. Smailagic and N. Ranganathan",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design",

note = "IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design ; Conference date: 11-05-2005 Through 12-05-2005",

}

Thondapu, C, Elakkumanan, P & Sridhar, R 2005, RG-SRAM: A low gate leakage memory design. in A Smailagic & N Ranganathan (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI, pp. 295-296, IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States, 05/11/05. https://doi.org/10.1109/ISVLSI.2005.64

RG-SRAM: A low gate leakage memory design. / Thondapu, Charan; Elakkumanan, Praveen; Sridhar, Ramalingam.
Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. ed. / A. Smailagic; N. Ranganathan. 2005. p. 295-296 (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - RG-SRAM

T2 - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design

AU - Thondapu, Charan

AU - Elakkumanan, Praveen

AU - Sridhar, Ramalingam

PY - 2005

Y1 - 2005

N2 - The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel Reduced-Gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in Very Deep Sub-Micron (VDSM) cache and embedded memories.

AB - The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel Reduced-Gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in Very Deep Sub-Micron (VDSM) cache and embedded memories.

UR - https://www.scopus.com/pages/publications/26844522441

U2 - 10.1109/ISVLSI.2005.64

DO - 10.1109/ISVLSI.2005.64

M3 - Conference contribution

AN - SCOPUS:26844522441

SN - 076952365X

SN - 9780769523651

T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

SP - 295

EP - 296

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design

A2 - Smailagic, A.

A2 - Ranganathan, N.

Y2 - 11 May 2005 through 12 May 2005

ER -

RG-SRAM: A low gate leakage memory design

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this