Rail-to-rail split-output SET tolerant digital gates

Electronic circuits operating in the radiation intensive environment like space, are subject to a barrage of cosmic particles like neutrons, protons, and heavy ions which can cause voltage glitches in various nodes of circuits causing single event upsets (SEUs) that can cause catastrophic failures. SEU tolerant circuits are required to improve reliability of electronic circuits in radiation prone environment. This paper proposes an improved split-output SEU tolerant logic gate whose outputs swing rail-to-rail thereby improving the noise-margin. The proposed design achieves equal delays for both the outputs thereby facilitating easier characterization of delays for creation of Synopsys Liberty timing libraries for seamless integration with the existing place-and-route tools. A standard-cell library comprising of inverter, two-input NAND, NOR, XOR, and XNOR, tri-state inverter, and D-flip-flops with set, reset, and both set-reset, were designed for various drive strengths in TSMC-28 nm and UMC-180-nm CMOS technology. The proposed logic gates have been simulated up to 120MeV-cm²/ mg of Linear Energy Transfer (LET) and have been found not to cause bit flips in the subsequent stage.