TY - GEN
T1 - PVT variations aware optimal sleep vector determination of dual VT domino or circuits
AU - Gong, Na
AU - Wang, Jinhui
AU - Sridhar, Ramalingam
PY - 2011
Y1 - 2011
N2 - In this paper, determining optimal leakage vector for dual Vt domino OR circuits is explored under process, supply voltage, and temperature (PVT) variations based on 65 nm bulk and 45 nm high k/metal gate (HK+MG) technologies, while considering design parameters, environmental parameters, working characteristics of circuits, and application cases. It concludes that the high clock signal with high inputs (CHIH) vector is the optimal sleep vector for practical low leakage register files applications, and the HK+MG technology further highlights the effectiveness of the CHIH vector as compared to other vectors.
AB - In this paper, determining optimal leakage vector for dual Vt domino OR circuits is explored under process, supply voltage, and temperature (PVT) variations based on 65 nm bulk and 45 nm high k/metal gate (HK+MG) technologies, while considering design parameters, environmental parameters, working characteristics of circuits, and application cases. It concludes that the high clock signal with high inputs (CHIH) vector is the optimal sleep vector for practical low leakage register files applications, and the HK+MG technology further highlights the effectiveness of the CHIH vector as compared to other vectors.
UR - https://www.scopus.com/pages/publications/84255195448
U2 - 10.1109/SOCC.2011.6085092
DO - 10.1109/SOCC.2011.6085092
M3 - Conference contribution
AN - SCOPUS:84255195448
SN - 9781457716164
T3 - International System on Chip Conference
SP - 359
EP - 364
BT - Proceedings - IEEE International SOC Conference, SOCC 2011
T2 - 24th IEEE International System on Chip Conference, SOCC 2011
Y2 - 26 September 2011 through 28 September 2011
ER -