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Processor assignment in heterogeneous parallel architectures

  • Daniel A. Menasce
  • , Stella C.S. Porto
  • , Satish K. Tripathi
  • University of Maryland, College Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

It has been already demonstrated that cost-effective multiprocessor designs may be obtained by combining in the same architecture processors of different speeds (heterogeneous architecture) so that the serial and critical portions of the application may benefit from a fast single processor. This paper presents a systematic way to build static heuristic scheduling algorithms for such environments. Several algorithms are proposed and their performance are compared through simulation. One of the proposed algorithms is shown to achieve substantial performance gains as the degree of heterogeneity of the architecture increases.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPubl by IEEE
Pages186-191
Number of pages6
ISBN (Print)0818626720
StatePublished - 1992
EventProceedings of the 6th International Parallel Processing Symposium - Beverly Hills, CA, USA
Duration: Mar 23 1992Mar 26 1992

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Conference

ConferenceProceedings of the 6th International Parallel Processing Symposium
CityBeverly Hills, CA, USA
Period03/23/9203/26/92

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