TY - GEN
T1 - Pre-ATPG path selection for near optimal post-ATPG process space coverage
AU - Xiong, Jinjun
AU - Shi, Yiyu
AU - Zolotov, Vladimir
AU - Visweswariah, Chandu
PY - 2009
Y1 - 2009
N2 - Path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. To guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. Existing coveragebased path selection techniques, however, suffer from the loss of coverage after ATPG (automatic test pattern generation), i.e., although the pre-ATPG path selection achieves good coverage, after ATPG, the coverage can be severely reduced as many paths turn out to be unsensitizable. This paper presents a novel path selection algorithm that, without running ATPG, selects a set of n paths to achieve near optimal post-ATPG coverage. Details of the algorithm and its optimality conditions are discussed. Experimental results show that, compared to the state-of-the-art, the proposed algorithm achieves not only superior post-ATPG coverage, but also significant runtime speedup.
AB - Path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. To guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. Existing coveragebased path selection techniques, however, suffer from the loss of coverage after ATPG (automatic test pattern generation), i.e., although the pre-ATPG path selection achieves good coverage, after ATPG, the coverage can be severely reduced as many paths turn out to be unsensitizable. This paper presents a novel path selection algorithm that, without running ATPG, selects a set of n paths to achieve near optimal post-ATPG coverage. Details of the algorithm and its optimality conditions are discussed. Experimental results show that, compared to the state-of-the-art, the proposed algorithm achieves not only superior post-ATPG coverage, but also significant runtime speedup.
KW - Optimality
KW - Path selection
KW - Process space coverage
UR - https://www.scopus.com/pages/publications/76349113813
U2 - 10.1145/1687399.1687419
DO - 10.1145/1687399.1687419
M3 - Conference contribution
AN - SCOPUS:76349113813
SN - 9781605588001
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 89
EP - 96
BT - Proceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, ICCAD 2009
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009
Y2 - 2 November 2009 through 5 November 2009
ER -