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Potential well engineering by partial oxidation of TiN for high-speed and low-voltage flash memory with good 125°C data retention and excellent endurance

  • Gang Zhang
  • , Chang Ho Ra
  • , Hua Min Li
  • , Cheng Yang
  • , Won Jong Yoo
  • Sungkyunkwan University
  • Korea Institute of Science and Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Potential well engineering is proposed for NAND Flash memory. With a variable (∼2nm-4.3nm) tunnel barrier, the engineered well (EW) enhances tunneling of carriers during program/erase (P/E) to result in fast P/E, while it suppresses charge loss under the retention mode to result in good data retention. The EWalso improves endurance, as it is insensitive to the P/E stress induced tunnel barrier degradation. The EW demonstrated in this work is formed by partial oxidation of TiN at the interfaces of the SiO2/TiN/SiO2 stack during rapid thermal process (RTP), and its band profile is characterized by XPS, TEM, internal photoemission (IPE), XRD, and band simulation. The memory devices with an EW show promising performances in fast program (<μs), low-voltage operation (6-8MV/cm), good 10-year data retention at 125°C, and excellent endurance (>107 P/E cycles).

Original languageEnglish
Title of host publication2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
Pages34.5.1-34.5.4
DOIs
StatePublished - 2009
Event2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States
Duration: Dec 7 2009Dec 9 2009

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2009 International Electron Devices Meeting, IEDM 2009
Country/TerritoryUnited States
CityBaltimore, MD
Period12/7/0912/9/09

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