@inproceedings{52fc858c1d764041a87ba2b2e0455a7d,
title = "Parallel MOSFET Module with Low Parasitic Inductance and Balanced Dynamic Current",
abstract = "Paralleling multiple MOSFETs is a common prac-tice to achieve high current carrying capability. This paper proposes a low-parasitic inductance parallel module design to enhance current sharing performance and low current measuring for normally-on MOSFETs. The module utilizes a laminated PCB structure to minimize parasitic inductance, thereby reducing voltage overshoot during switching and ensuring balanced cur-rent distribution between parallel devices. A symmetric layout is incorporated to achieve equal gate and source impedance, significantly improving dynamic current sharing. The LTspice simulation and experimental results from double pulse tests (DPT) confirm that the proposed design successfully reduces parasitic effects and improves current balancing, making it well-suited for high-power applications.",
keywords = "Current balancing, MOS-FET, parallel connection",
author = "Ge Yang and Arindam Sircar and Wei Liu and Xiu Yao",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 17th Annual IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025 ; Conference date: 19-10-2025 Through 23-10-2025",
year = "2025",
doi = "10.1109/ECCE58356.2025.11260247",
language = "English",
series = "2025 IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2025 IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025",
address = "United States",
}