TY - GEN
T1 - Optimization and predication of leakage current characteristics in wide domino or gates under PVT variation
AU - Gong, Na
AU - Sridhar, Ramalingam
PY - 2010
Y1 - 2010
N2 - The leakage current characteristics of wide dual Vt domino OR gates is studied and gate-level models for estimating sub-threshold leakage and gate leakage current with two different sleep states are developed to determine the optimal sleep state. Results demonstrate that the developed models are robust and exhibit maximum error of 4% with respect to device-level BSIM4 models based HSPICE simulations. Furthermore, PVT variation aware leakage current characteristics of domino OR gates is analyzed and the optimal sleep state is obtained.
AB - The leakage current characteristics of wide dual Vt domino OR gates is studied and gate-level models for estimating sub-threshold leakage and gate leakage current with two different sleep states are developed to determine the optimal sleep state. Results demonstrate that the developed models are robust and exhibit maximum error of 4% with respect to device-level BSIM4 models based HSPICE simulations. Furthermore, PVT variation aware leakage current characteristics of domino OR gates is analyzed and the optimal sleep state is obtained.
UR - https://www.scopus.com/pages/publications/79960731614
U2 - 10.1109/SOCC.2010.5784663
DO - 10.1109/SOCC.2010.5784663
M3 - Conference contribution
AN - SCOPUS:79960731614
SN - 9781424466832
T3 - Proceedings - IEEE International SOC Conference, SOCC 2010
SP - 19
EP - 24
BT - Proceedings - IEEE International SOC Conference, SOCC 2010
T2 - 23rd IEEE International SOC Conference, SOCC 2010
Y2 - 27 September 2010 through 29 September 2010
ER -