On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

Alfonso Martinez-Smith; Ramalingam Sridhar

On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

Alfonso Martinez-Smith
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a design style.

Original language	English
Pages (from-to)	57-60
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - 1996
Event	Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: Sep 23 1996 → Sep 27 1996

Cite this

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title = "On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits",

abstract = "Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a design style.",

author = "Alfonso Martinez-Smith and Ramalingam Sridhar",

year = "1996",

language = "English",

pages = "57--60",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 23-09-1996 Through 27-09-1996",

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TY - JOUR

T1 - On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

AU - Martinez-Smith, Alfonso

AU - Sridhar, Ramalingam

PY - 1996

Y1 - 1996

N2 - Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a design style.

AB - Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a design style.

UR - https://www.scopus.com/pages/publications/0029726312

M3 - Conference article

AN - SCOPUS:0029726312

SN - 1063-0988

SP - 57

EP - 60

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit

Y2 - 23 September 1996 through 27 September 1996

ER -

On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

Abstract

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