A multidecoder design for programmable logic array (PLA) devices is introduced and found to be superior to both two-decoder ROM and single-decoder PLA devices in implementing a special class of Boolean expressions. In this class the logic expressions may be lengthy but are restricted in the number of input variables comprising each p-term. A theoretical analysis of the area efficiency of the design is supplemented by CAD design examples that verify its superiority. Implementation of the multidecoder design using three-dimensional microcircuit topography to attain even greater savings in area and speed is considered.