TY - GEN
T1 - New framework for automatic generation, insertion and verification of memory built-in self test units
AU - Zarrineh, Kamran
AU - Upadhyaya, Shambhu J.
PY - 1999
Y1 - 1999
N2 - The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized.
AB - The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized.
UR - https://www.scopus.com/pages/publications/0032663590
M3 - Conference contribution
AN - SCOPUS:0032663590
SN - 076950146X
T3 - Proceedings of the IEEE VLSI Test Symposium
SP - 391
EP - 396
BT - Proceedings of the IEEE VLSI Test Symposium
PB - IEEE
T2 - Proceedings of the 1999 17th IEEE VLSI Test Symposium (VTS'99)
Y2 - 25 April 1999 through 29 April 1999
ER -