Multipliers based on the Interlaced Carry Arrest Addition

Uttam Kumar; Adly T. Fam

doi:10.1109/MWSCAS48704.2020.9184570

Multipliers based on the Interlaced Carry Arrest Addition

Uttam Kumar
, Adly T. Fam

Department of Electrical Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Proposed here are multipliers based on interlaced carry arrest addition. These multipliers save, in VLSI simulations, up to 27% in average power, in comparison to the Wallace tree multipliers, with only a small increase in latency.

Original language	English
Title of host publication	2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1088-1091
Number of pages	4
ISBN (Electronic)	9781538629161
DOIs	https://doi.org/10.1109/MWSCAS48704.2020.9184570
State	Published - Aug 2020
Event	63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Springfield, United States Duration: Aug 9 2020 → Aug 12 2020

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2020-August
ISSN (Print)	1548-3746

Conference

Conference	63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020
Country/Territory	United States
City	Springfield
Period	08/9/20 → 08/12/20

Access to Document

10.1109/MWSCAS48704.2020.9184570

Cite this

Kumar, U., & Fam, A. T. (2020). Multipliers based on the Interlaced Carry Arrest Addition. In 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings (pp. 1088-1091). Article 9184570 (Midwest Symposium on Circuits and Systems; Vol. 2020-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS48704.2020.9184570

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title = "Multipliers based on the Interlaced Carry Arrest Addition",

abstract = "Proposed here are multipliers based on interlaced carry arrest addition. These multipliers save, in VLSI simulations, up to 27\% in average power, in comparison to the Wallace tree multipliers, with only a small increase in latency.",

author = "Uttam Kumar and Fam, \{Adly T.\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020 ; Conference date: 09-08-2020 Through 12-08-2020",

year = "2020",

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doi = "10.1109/MWSCAS48704.2020.9184570",

language = "English",

series = "Midwest Symposium on Circuits and Systems",

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Kumar, U & Fam, AT 2020, Multipliers based on the Interlaced Carry Arrest Addition. in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings., 9184570, Midwest Symposium on Circuits and Systems, vol. 2020-August, Institute of Electrical and Electronics Engineers Inc., pp. 1088-1091, 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, United States, 08/9/20. https://doi.org/10.1109/MWSCAS48704.2020.9184570

Multipliers based on the Interlaced Carry Arrest Addition. / Kumar, Uttam; Fam, Adly T.
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. p. 1088-1091 9184570 (Midwest Symposium on Circuits and Systems; Vol. 2020-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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M3 - Conference contribution

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BT - 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings

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Multipliers based on the Interlaced Carry Arrest Addition

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