Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

Rui Zhang; Taizhi Liu; Kexin Yang; Linda Milor

doi:10.1109/IIRW.2017.8361243

Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

Rui Zhang
, Taizhi Liu
, Kexin Yang
, Linda Milor

Department of Electrical Engineering

Georgia Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

Bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD) degrade the performance of circuits, such as FinFET-based SRAMs. In this paper, a unified modeling methodology is applied for SRAM reliability degradation due to BTI and HCI, which are implemented with a time-dependent threshold voltage model, and GOBD which is implemented with a comprehensive current model. The applicability of degradation models is verified through fitting and comparison with the measured results. SRAM cell lifetime due to different mechanisms is calculated with Monte Carlo simulations to determine the performance degradation. The combined lifetime distribution and failure probability of an SRAM is further analyzed while considering the effect of Error Correcting Codes (ECC). Based on the different degrees of sensitivity, the potential of designing optimal accelerated life tests due to different failure mechanisms is discussed.

Original language	English
Title of host publication	2017 IEEE International Integrated Reliability Workshop, IIRW 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538623329
DOIs	https://doi.org/10.1109/IIRW.2017.8361243
State	Published - Jul 2 2017
Event	2017 IEEE International Integrated Reliability Workshop, IIRW 2017 - South Lake Tahoe, United States Duration: Oct 8 2017 → Oct 12 2017

Publication series

Name	IEEE International Integrated Reliability Workshop Final Report
Volume	2017-October
ISSN (Print)	1930-8841
ISSN (Electronic)	2374-8036

Conference

Conference	2017 IEEE International Integrated Reliability Workshop, IIRW 2017
Country/Territory	United States
City	South Lake Tahoe
Period	10/8/17 → 10/12/17

Keywords

Bias temperature instability
Error Correcting Codes
FinFET
Gate oxide breakdown
Hot carrier injection
Performance
Reliability
SRAM

Access to Document

10.1109/IIRW.2017.8361243

Cite this

Zhang, R., Liu, T., Yang, K., & Milor, L. (2017). Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown. In 2017 IEEE International Integrated Reliability Workshop, IIRW 2017 (pp. 1-4). (IEEE International Integrated Reliability Workshop Final Report; Vol. 2017-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IIRW.2017.8361243

Zhang, Rui ; Liu, Taizhi ; Yang, Kexin et al. / Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown. 2017 IEEE International Integrated Reliability Workshop, IIRW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-4 (IEEE International Integrated Reliability Workshop Final Report).

@inproceedings{aac181ed04e24314a872763e967018be,

title = "Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown",

abstract = "Bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD) degrade the performance of circuits, such as FinFET-based SRAMs. In this paper, a unified modeling methodology is applied for SRAM reliability degradation due to BTI and HCI, which are implemented with a time-dependent threshold voltage model, and GOBD which is implemented with a comprehensive current model. The applicability of degradation models is verified through fitting and comparison with the measured results. SRAM cell lifetime due to different mechanisms is calculated with Monte Carlo simulations to determine the performance degradation. The combined lifetime distribution and failure probability of an SRAM is further analyzed while considering the effect of Error Correcting Codes (ECC). Based on the different degrees of sensitivity, the potential of designing optimal accelerated life tests due to different failure mechanisms is discussed.",

keywords = "Bias temperature instability, Error Correcting Codes, FinFET, Gate oxide breakdown, Hot carrier injection, Performance, Reliability, SRAM",

author = "Rui Zhang and Taizhi Liu and Kexin Yang and Linda Milor",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Integrated Reliability Workshop, IIRW 2017 ; Conference date: 08-10-2017 Through 12-10-2017",

year = "2017",

month = jul,

day = "2",

doi = "10.1109/IIRW.2017.8361243",

language = "English",

series = "IEEE International Integrated Reliability Workshop Final Report",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "2017 IEEE International Integrated Reliability Workshop, IIRW 2017",

address = "United States",

}

Zhang, R, Liu, T, Yang, K & Milor, L 2017, Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown. in 2017 IEEE International Integrated Reliability Workshop, IIRW 2017. IEEE International Integrated Reliability Workshop Final Report, vol. 2017-October, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2017 IEEE International Integrated Reliability Workshop, IIRW 2017, South Lake Tahoe, United States, 10/8/17. https://doi.org/10.1109/IIRW.2017.8361243

Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown. / Zhang, Rui; Liu, Taizhi; Yang, Kexin et al.
2017 IEEE International Integrated Reliability Workshop, IIRW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-4 (IEEE International Integrated Reliability Workshop Final Report; Vol. 2017-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

AU - Zhang, Rui

AU - Liu, Taizhi

AU - Yang, Kexin

AU - Milor, Linda

PY - 2017/7/2

Y1 - 2017/7/2

N2 - Bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD) degrade the performance of circuits, such as FinFET-based SRAMs. In this paper, a unified modeling methodology is applied for SRAM reliability degradation due to BTI and HCI, which are implemented with a time-dependent threshold voltage model, and GOBD which is implemented with a comprehensive current model. The applicability of degradation models is verified through fitting and comparison with the measured results. SRAM cell lifetime due to different mechanisms is calculated with Monte Carlo simulations to determine the performance degradation. The combined lifetime distribution and failure probability of an SRAM is further analyzed while considering the effect of Error Correcting Codes (ECC). Based on the different degrees of sensitivity, the potential of designing optimal accelerated life tests due to different failure mechanisms is discussed.

AB - Bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD) degrade the performance of circuits, such as FinFET-based SRAMs. In this paper, a unified modeling methodology is applied for SRAM reliability degradation due to BTI and HCI, which are implemented with a time-dependent threshold voltage model, and GOBD which is implemented with a comprehensive current model. The applicability of degradation models is verified through fitting and comparison with the measured results. SRAM cell lifetime due to different mechanisms is calculated with Monte Carlo simulations to determine the performance degradation. The combined lifetime distribution and failure probability of an SRAM is further analyzed while considering the effect of Error Correcting Codes (ECC). Based on the different degrees of sensitivity, the potential of designing optimal accelerated life tests due to different failure mechanisms is discussed.

KW - Bias temperature instability

KW - Error Correcting Codes

KW - FinFET

KW - Gate oxide breakdown

KW - Hot carrier injection

KW - Performance

KW - Reliability

KW - SRAM

UR - https://www.scopus.com/pages/publications/85047801646

U2 - 10.1109/IIRW.2017.8361243

DO - 10.1109/IIRW.2017.8361243

M3 - Conference contribution

AN - SCOPUS:85047801646

T3 - IEEE International Integrated Reliability Workshop Final Report

SP - 1

EP - 4

BT - 2017 IEEE International Integrated Reliability Workshop, IIRW 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE International Integrated Reliability Workshop, IIRW 2017

Y2 - 8 October 2017 through 12 October 2017

ER -

Zhang R, Liu T, Yang K, Milor L. Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown. In 2017 IEEE International Integrated Reliability Workshop, IIRW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-4. (IEEE International Integrated Reliability Workshop Final Report). doi: 10.1109/IIRW.2017.8361243

Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this