Modeling of FinFET SRAM array reliability degradation due to electromigration

Effective assessment of degradation induced by electromigration (EM) is necessary for the design of reliable circuits based on FinFET technology. In this paper, a new methodology is proposed where FinFET SRAM cell array activity is used to evaluate the resistance degradation due to EM. The implementation of this methodology consists of analysis of stress evolution, a time-dependent resistance model, cell array activity extraction, and a customized algorithm for cell array reliability evaluation. The stress model is derived from the material transport equation which contains the driving forces due to the gradient of vacancy concentration, temperature, hydrostatic stress, and EM itself. The time-dependent resistance shift describes the effect of stress evolution. The customized algorithm is applied to calculate the resistance degradation while considering the characteristics of metal wire arrays in SRAMs. The statistical degradation in a FinFET SRAM cell array reveals that, for the tested case, in addition to the percentage of the workload in various operating modes, the cell array activity distribution also affects EM degradation. More evenly distributed cell activity results in better EM reliability.