Mitigating Gate Resistance in 180 nm CMOS High-Frequency LC-VCOs: Enhanced Performance and Simulation-Model Validation

This article presents a detailed analysis of the impact of gate resistance in the inductor-capacitor (LC)-voltage-controlled oscillator (VCO) core. A design guideline centered on the multifinger MOSFET in higher technology nodes (≥90 nm) is proposed to improve the swing and phase noise (PN) of the VCO. As proof of concept, a high-frequency LC-VCO operating from 6.8 to 8.2 GHz using a 5-bit binary-weighted switched capacitor control is realized in UMC 180 nm CMOS. A PN of −108.64 dBc/Hz is achieved at 1 MHz offset for the 7.2 GHz band. The VCO has a tuning range (TR) of 18.66% and a figure-of-merit (FoM) of 177.5 dB, consuming 6.7 mW of power when operating from a 1.8 V supply and occupying a 0.2 mm² area.