Minimizing concurrent test time in SoC's by balancing resource usage

Dan Zhao; Shambhu Upadhyaya; Martin Margala

doi:10.1145/505306.505323

Minimizing concurrent test time in SoC's by balancing resource usage

Dan Zhao
, Shambhu Upadhyaya
, Martin Margala

Department of Computer Science and Engineering

SUNY Buffalo
University of Rochester

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

We present a novel test scheduling algorithm for embedded corebased SoC's. Given a system integrated with a set of cores and a set of test resources, we select a test for each core from a set of alternative test sets, and schedule it in a way that evenly balances the resource usage, and ultimately reduce the test application time. Furthermore, we propose a novel approach that groups the cores and assigns higher priority to those with smaller number of alternate test sets. In addition, we also extend the algorithm to allow multiple test sets selection from a set of alternatives to facilitate testing for various fault models.

Original language	English
Title of host publication	GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery, Inc
Pages	77-82
Number of pages	6
ISBN (Electronic)	1581134622, 9781581134629
DOIs	https://doi.org/10.1145/505306.505323
State	Published - Apr 18 2002
Event	12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002 - New York, United States Duration: Apr 18 2002 → Apr 19 2002

Publication series

Name	GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Conference

Conference	12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002
Country/Territory	United States
City	New York
Period	04/18/02 → 04/19/02

Keywords

Resource balancing
System-on-a-chip test scheduling
Test sets selection

Access to Document

10.1145/505306.505323

Cite this

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title = "Minimizing concurrent test time in SoC's by balancing resource usage",

abstract = "We present a novel test scheduling algorithm for embedded corebased SoC's. Given a system integrated with a set of cores and a set of test resources, we select a test for each core from a set of alternative test sets, and schedule it in a way that evenly balances the resource usage, and ultimately reduce the test application time. Furthermore, we propose a novel approach that groups the cores and assigns higher priority to those with smaller number of alternate test sets. In addition, we also extend the algorithm to allow multiple test sets selection from a set of alternatives to facilitate testing for various fault models.",

keywords = "Resource balancing, System-on-a-chip test scheduling, Test sets selection",

author = "Dan Zhao and Shambhu Upadhyaya and Martin Margala",

year = "2002",

month = apr,

day = "18",

doi = "10.1145/505306.505323",

language = "English",

series = "GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI",

publisher = "Association for Computing Machinery, Inc",

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booktitle = "GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI",

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Zhao, D, Upadhyaya, S & Margala, M 2002, Minimizing concurrent test time in SoC's by balancing resource usage. in GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI. GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI, Association for Computing Machinery, Inc, pp. 77-82, 12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002, New York, United States, 04/18/02. https://doi.org/10.1145/505306.505323

Minimizing concurrent test time in SoC's by balancing resource usage. / Zhao, Dan; Upadhyaya, Shambhu; Margala, Martin.
GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI. Association for Computing Machinery, Inc, 2002. p. 77-82 (GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Minimizing concurrent test time in SoC's by balancing resource usage

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AU - Upadhyaya, Shambhu

AU - Margala, Martin

PY - 2002/4/18

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N2 - We present a novel test scheduling algorithm for embedded corebased SoC's. Given a system integrated with a set of cores and a set of test resources, we select a test for each core from a set of alternative test sets, and schedule it in a way that evenly balances the resource usage, and ultimately reduce the test application time. Furthermore, we propose a novel approach that groups the cores and assigns higher priority to those with smaller number of alternate test sets. In addition, we also extend the algorithm to allow multiple test sets selection from a set of alternatives to facilitate testing for various fault models.

AB - We present a novel test scheduling algorithm for embedded corebased SoC's. Given a system integrated with a set of cores and a set of test resources, we select a test for each core from a set of alternative test sets, and schedule it in a way that evenly balances the resource usage, and ultimately reduce the test application time. Furthermore, we propose a novel approach that groups the cores and assigns higher priority to those with smaller number of alternate test sets. In addition, we also extend the algorithm to allow multiple test sets selection from a set of alternatives to facilitate testing for various fault models.

KW - Resource balancing

KW - System-on-a-chip test scheduling

KW - Test sets selection

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DO - 10.1145/505306.505323

M3 - Conference contribution

AN - SCOPUS:0038111322

T3 - GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

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BT - GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

PB - Association for Computing Machinery, Inc

T2 - 12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002

Y2 - 18 April 2002 through 19 April 2002

ER -

Minimizing concurrent test time in SoC's by balancing resource usage

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Keywords

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