TY - GEN
T1 - Low power tri-state register files design for modern out-of-order processors
AU - Gong, Na
AU - Tang, Geng
AU - Wang, Jinhui
AU - Sridhar, Ramalingam
PY - 2011
Y1 - 2011
N2 - In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7-14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4-17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.
AB - In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7-14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4-17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.
UR - https://www.scopus.com/pages/publications/84255175746
U2 - 10.1109/SOCC.2011.6085113
DO - 10.1109/SOCC.2011.6085113
M3 - Conference contribution
AN - SCOPUS:84255175746
SN - 9781457716164
T3 - International System on Chip Conference
SP - 323
EP - 328
BT - Proceedings - IEEE International SOC Conference, SOCC 2011
T2 - 24th IEEE International System on Chip Conference, SOCC 2011
Y2 - 26 September 2011 through 28 September 2011
ER -