Local clocking approach for self-timed datapath designs

Seokjin Kim; Ramalingam Sridhar

Local clocking approach for self-timed datapath designs

Seokjin Kim
, Ramalingam Sridhar

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper presents the design and analysis of a local clock control circuit for the use of synchronous datapaths in asynchronous environment. The design and the detailed simulation results of the circuit are given. A locally-clocked multiplier is designed and compared with several asynchronous implementations. The circuit provides an efficient method of asynchronous system implementation, using synchronous datapaths.

Original language	English
Pages (from-to)	152-155
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
State	Published - 1995
Event	Proceedings of the 5th Great Lakes Symposium on VLSI - Buffalo, NY, USA Duration: Mar 16 1995 → Mar 18 1995

Cite this

@article{260b94c8229841bc871122b9492a6637,

title = "Local clocking approach for self-timed datapath designs",

abstract = "This paper presents the design and analysis of a local clock control circuit for the use of synchronous datapaths in asynchronous environment. The design and the detailed simulation results of the circuit are given. A locally-clocked multiplier is designed and compared with several asynchronous implementations. The circuit provides an efficient method of asynchronous system implementation, using synchronous datapaths.",

author = "Seokjin Kim and Ramalingam Sridhar",

year = "1995",

language = "English",

pages = "152--155",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

note = "Proceedings of the 5th Great Lakes Symposium on VLSI ; Conference date: 16-03-1995 Through 18-03-1995",

}

TY - JOUR

T1 - Local clocking approach for self-timed datapath designs

AU - Kim, Seokjin

AU - Sridhar, Ramalingam

PY - 1995

Y1 - 1995

N2 - This paper presents the design and analysis of a local clock control circuit for the use of synchronous datapaths in asynchronous environment. The design and the detailed simulation results of the circuit are given. A locally-clocked multiplier is designed and compared with several asynchronous implementations. The circuit provides an efficient method of asynchronous system implementation, using synchronous datapaths.

AB - This paper presents the design and analysis of a local clock control circuit for the use of synchronous datapaths in asynchronous environment. The design and the detailed simulation results of the circuit are given. A locally-clocked multiplier is designed and compared with several asynchronous implementations. The circuit provides an efficient method of asynchronous system implementation, using synchronous datapaths.

UR - https://www.scopus.com/pages/publications/0029225399

M3 - Conference article

AN - SCOPUS:0029225399

SN - 1066-1395

SP - 152

EP - 155

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 5th Great Lakes Symposium on VLSI

Y2 - 16 March 1995 through 18 March 1995

ER -

Local clocking approach for self-timed datapath designs

Abstract

Other files and links

Fingerprint

Cite this