TY - GEN
T1 - Leakage aware ser reduction technique for UDSM logic circuits
AU - Elakkumanan, Praveen
AU - Ananthakrishnan, Vishwanath
AU - Narasimhan, Ashok
AU - Sridhar, Ramalingam
PY - 2004
Y1 - 2004
N2 - With technology scaling aggressively into the very deep submicron era, leakage power and Single Event Upsets (SEUs) pose serious challenges to circuit designers. Here, we present a novel technique to reduce the Soft Error Rate (SER) in combinational circuits, with minimal area overhead using Minimum Leakage Input Vector (MLIV) leakage reduction technique. Simulation results show significant reduction in area overhead as compared to existing techniques, while reducing the leakage power by nearly 40%.
AB - With technology scaling aggressively into the very deep submicron era, leakage power and Single Event Upsets (SEUs) pose serious challenges to circuit designers. Here, we present a novel technique to reduce the Soft Error Rate (SER) in combinational circuits, with minimal area overhead using Minimum Leakage Input Vector (MLIV) leakage reduction technique. Simulation results show significant reduction in area overhead as compared to existing techniques, while reducing the leakage power by nearly 40%.
KW - Leakage power
KW - Reliability
KW - SEU
KW - Soft errors
KW - Ultra deep submicron design
UR - https://www.scopus.com/pages/publications/14844325748
M3 - Conference contribution
AN - SCOPUS:14844325748
SN - 0780384458
SN - 9780780384453
T3 - Proceedings - IEEE International SOC Conference
SP - 82
EP - 85
BT - Proceedings - IEEE International SOC Conference
A2 - Chickanosky, J.
A2 - Ha, D.
A2 - Auletta, R.
T2 - Proceedings - IEEE International SOC Conference
Y2 - 12 September 2004 through 15 September 2004
ER -