Interlaced Partition Multiplier

Christopher Fritz; Adly T. Fam

doi:10.1109/TC.2015.2481379

Interlaced Partition Multiplier

Christopher Fritz
, Adly T. Fam

Department of Electrical Engineering

SUNY Buffalo

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

A new apparatus for fast multiplication of two numbers is introduced. Inputs are split into partitions, and one number is replaced by two with zeros interlaced in every other partition. Products are computed with no carries between partitions, in the time required to multiply the short partitions and add the partial sums. Component adders and multipliers can be chosen to trade off area and speed. A new graphical tool is used to compare this multiplier to existing ones based on CMOS VLSI simulations.

Original language	English
Article number	7274668
Pages (from-to)	2672-2677
Number of pages	6
Journal	IEEE Transactions on Computers
Volume	65
Issue number	8
DOIs	https://doi.org/10.1109/TC.2015.2481379
State	Published - Aug 1 2016

Keywords

Algorithms
CMOS
cost/performance
high-speed arithmetic
multiplier
VLSI

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10.1109/TC.2015.2481379

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KW - cost/performance

KW - high-speed arithmetic

KW - multiplier

KW - VLSI

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Interlaced Partition Multiplier

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Keywords

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