TY - GEN
T1 - Incremental criticality and yield gradients
AU - Xiong, Jinjun
AU - Zolotov, Vladimir
AU - Visweswariah, Chandu
PY - 2008
Y1 - 2008
N2 - Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing optimization and timing-driven physical synthesis. Existing work in the literature, however, computes both metrics in a non-incremental manner, i.e., after one or more changes are made in a previously-timed circuit, both metrics need to be recomputed from scratch, which is obviously undesirable for optimizing large circuits. The major contribution of this paper is to propose two novel techniques to compute both criticality and yield gradients efficiently and incrementally. In addition, while node and edge criticalities are addressed in the literature, this paper for the first time describes a technique to compute path criticalities. To further improve algorithmic efficiency, this paper also proposes a novel technique to update "chip slack" incrementally. Numerical results show our methods to be over two orders of magnitude faster than previous work.
AB - Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing optimization and timing-driven physical synthesis. Existing work in the literature, however, computes both metrics in a non-incremental manner, i.e., after one or more changes are made in a previously-timed circuit, both metrics need to be recomputed from scratch, which is obviously undesirable for optimizing large circuits. The major contribution of this paper is to propose two novel techniques to compute both criticality and yield gradients efficiently and incrementally. In addition, while node and edge criticalities are addressed in the literature, this paper for the first time describes a technique to compute path criticalities. To further improve algorithmic efficiency, this paper also proposes a novel technique to update "chip slack" incrementally. Numerical results show our methods to be over two orders of magnitude faster than previous work.
UR - https://www.scopus.com/pages/publications/49749131157
U2 - 10.1109/DATE.2008.4484830
DO - 10.1109/DATE.2008.4484830
M3 - Conference contribution
AN - SCOPUS:49749131157
SN - 9783981080
SN - 9789783981089
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1130
EP - 1135
BT - Design, Automation and Test in Europe, DATE 2008
T2 - Design, Automation and Test in Europe, DATE 2008
Y2 - 10 March 2008 through 14 March 2008
ER -