Impact of front-end wearout mechanisms on FinFET SRAM soft error rate

We build a modelling and simulation flow to study how the front-end wearout mechanisms affect the FinFET SRAM soft error rate. This flow incorporates process variation, such as device dimensions, and degradation parameters. We first checked the impact of process parameters on critical charge and soft error rate. It is found that a larger gate length and higher temperature help us obtain better reliability for a FinFET SRAM cell under radiation, with a higher Q_crit and lower SER. Then, the time-dependent shift of Q_crit and SER is displayed. Within its range between 0% and 50%, a lower duty ratio leads to worse reliability due to soft errors. Moreover, a higher transition rate causes worse reliability.