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High speed robust current sense amplifier for nanoscale memories:- A winner take all approach

  • SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

The design of fast, low power and robust sense amplifier circuits is a challenge for nanoscale SRAMs due to the increasing bitline capacitance and process variations. Current sensing in SRAMs is promising to achieve high-speed operation in low-voltage application. In this paper, we propose a process variation tolerant, high performance and scalable current sense amplifier that uses a Winner Take All (WTA) approach for nanoscale SRAMs. Simulation of worst-case threshold voltage mismatch on our WTA sense amplifier shows that it could tolerate upto 10% variation in the threshold voltage, which is expected within die in a 70nm process. Detailed analysis of variation in the effective channel length (L eff) and supply voltage variation are also presented. A comparison of the sensing delay and energy consumption in 70nm technology shows that our WTA sense amplifier provides around 70-80% improvement in the sensing speed and consumes 28-70% less energy than the traditional voltage mode and current sense amplifiers.

Original languageEnglish
Title of host publicationProceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Pages569-574
Number of pages6
DOIs
StatePublished - 2006
Event19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design - Hyderabad, India
Duration: Jan 3 2006Jan 7 2006

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2006
ISSN (Print)1063-9667

Conference

Conference19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Country/TerritoryIndia
CityHyderabad
Period01/3/0601/7/06

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