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Hardware Design Rule Checker Using a CAM Architecture

  • SUNY Buffalo

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a hardware implementation of design rule checker using a specialized Content Addressable Memory (CAM) for the Manhattan geometric designs. Two dimensional relationships between rectangular objects in a design are checked with one dimensional design rules. The input data is processed by the pixel pre-processor in such a way that direct comparison between the input data and the stored rules in the CAM is possible. The comparison by the CAM reduces the number of memory references and logic operations of pattern matching and the simple architecture of the system enables a low cost implementation.

Original languageEnglish
Pages (from-to)141-147
Number of pages7
JournalVLSI Design
Volume4
Issue number2
DOIs
StatePublished - 1996

Keywords

  • Content Addressable memory
  • Design rule check
  • Hardware accelerator

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