Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Kexin Yang; Taizhi Liu; Rui Zhang; Dae Hyun Kim; Linda Milor

doi:10.1016/j.microrel.2017.06.038

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Kexin Yang
, Taizhi Liu
, Rui Zhang
, Dae Hyun Kim
, Linda Milor

Department of Electrical Engineering

Georgia Institute of Technology

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.

Original language	English
Pages (from-to)	81-86
Number of pages	6
Journal	Microelectronics Reliability
Volume	76-77
DOIs	https://doi.org/10.1016/j.microrel.2017.06.038
State	Published - Sep 2017

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10.1016/j.microrel.2017.06.038

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@article{f540fefd1aa24ea8a3a8f4285609123f,

title = "Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits",

abstract = "This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.",

author = "Kexin Yang and Taizhi Liu and Rui Zhang and Kim, \{Dae Hyun\} and Linda Milor",

note = "Publisher Copyright: {\textcopyright} 2017 Elsevier Ltd",

year = "2017",

month = sep,

doi = "10.1016/j.microrel.2017.06.038",

language = "English",

volume = "76-77",

pages = "81--86",

journal = "Microelectronics Reliability",

issn = "0026-2714",

publisher = "Elsevier Ltd",

}

TY - JOUR

T1 - Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

AU - Yang, Kexin

AU - Liu, Taizhi

AU - Zhang, Rui

AU - Kim, Dae Hyun

AU - Milor, Linda

PY - 2017/9

Y1 - 2017/9

N2 - This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.

AB - This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.

UR - https://www.scopus.com/pages/publications/85021338678

U2 - 10.1016/j.microrel.2017.06.038

DO - 10.1016/j.microrel.2017.06.038

M3 - Article

AN - SCOPUS:85021338678

SN - 0026-2714

VL - 76-77

SP - 81

EP - 86

JO - Microelectronics Reliability

JF - Microelectronics Reliability

ER -

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Abstract

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