FPGA-based point pattern matching processor with application to fingerprint matching

Nalini K. Ratha; Anil K. Jain; Diane T. Rover

FPGA-based point pattern matching processor with application to fingerprint matching

Nalini K. Ratha
, Anil K. Jain
, Diane T. Rover

Department of Computer Science and Engineering

Michigan State University

Research output: Contribution to conference › Paper › peer-review

7 Scopus citations

Abstract

We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to fingerprint matching using Splash 2 - an attached processor for SUN SPARCstation hosts. Each of the field programmable gate array (FPGA) - based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is verified. The final control bit stream for the PEs is generated using the synthesis tools. The point feature matching coprocessor can run at a peak speed of 17.1 MHz per feature vector of a fingerprint. With 65 features per fingerprint, the matching speed has been projected at the rate of 2.6 * 10⁵ fingerprints/sec. The synthesized coprocessor was tested on a 10,000 fingerprint database.

Original language	English
Pages	394-401
Number of pages	8
State	Published - 1995
Event	Proceedings of the Conference on Computer Architectures for Machine Perception, CAMP'95. - Como, Italy Duration: Sep 18 1995 → Sep 20 1995

Conference

Conference	Proceedings of the Conference on Computer Architectures for Machine Perception, CAMP'95.
City	Como, Italy
Period	09/18/95 → 09/20/95

Cite this

@conference{fbe886e276964640816ee37c887543ce,

title = "FPGA-based point pattern matching processor with application to fingerprint matching",

abstract = "We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to fingerprint matching using Splash 2 - an attached processor for SUN SPARCstation hosts. Each of the field programmable gate array (FPGA) - based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is verified. The final control bit stream for the PEs is generated using the synthesis tools. The point feature matching coprocessor can run at a peak speed of 17.1 MHz per feature vector of a fingerprint. With 65 features per fingerprint, the matching speed has been projected at the rate of 2.6 * 105 fingerprints/sec. The synthesized coprocessor was tested on a 10,000 fingerprint database.",

author = "Ratha, \{Nalini K.\} and Jain, \{Anil K.\} and Rover, \{Diane T.\}",

year = "1995",

language = "English",

pages = "394--401",

note = "Proceedings of the Conference on Computer Architectures for Machine Perception, CAMP'95. ; Conference date: 18-09-1995 Through 20-09-1995",

}

TY - CONF

T1 - FPGA-based point pattern matching processor with application to fingerprint matching

AU - Ratha, Nalini K.

AU - Jain, Anil K.

AU - Rover, Diane T.

PY - 1995

Y1 - 1995

N2 - We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to fingerprint matching using Splash 2 - an attached processor for SUN SPARCstation hosts. Each of the field programmable gate array (FPGA) - based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is verified. The final control bit stream for the PEs is generated using the synthesis tools. The point feature matching coprocessor can run at a peak speed of 17.1 MHz per feature vector of a fingerprint. With 65 features per fingerprint, the matching speed has been projected at the rate of 2.6 * 105 fingerprints/sec. The synthesized coprocessor was tested on a 10,000 fingerprint database.

AB - We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to fingerprint matching using Splash 2 - an attached processor for SUN SPARCstation hosts. Each of the field programmable gate array (FPGA) - based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is verified. The final control bit stream for the PEs is generated using the synthesis tools. The point feature matching coprocessor can run at a peak speed of 17.1 MHz per feature vector of a fingerprint. With 65 features per fingerprint, the matching speed has been projected at the rate of 2.6 * 105 fingerprints/sec. The synthesized coprocessor was tested on a 10,000 fingerprint database.

UR - https://www.scopus.com/pages/publications/0029532544

M3 - Paper

AN - SCOPUS:0029532544

SP - 394

EP - 401

T2 - Proceedings of the Conference on Computer Architectures for Machine Perception, CAMP'95.

Y2 - 18 September 1995 through 20 September 1995

ER -

FPGA-based point pattern matching processor with application to fingerprint matching

Abstract

Conference

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