FPGA-based high performance page layout segmentation

N. K. Ratha; A. K. Jain; D. T. Rover

FPGA-based high performance page layout segmentation

N. K. Ratha
, A. K. Jain
, D. T. Rover

Department of Computer Science and Engineering

Michigan State University

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2 - an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1.024 × 1.024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.

Original language	English
Pages (from-to)	29-34
Number of pages	6
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
State	Published - 1996
Event	Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA Duration: Mar 22 1996 → Mar 23 1996

Cite this

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title = "FPGA-based high performance page layout segmentation",

abstract = "A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2 - an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1.024 × 1.024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.",

author = "Ratha, \{N. K.\} and Jain, \{A. K.\} and Rover, \{D. T.\}",

year = "1996",

language = "English",

pages = "29--34",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

note = "Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI ; Conference date: 22-03-1996 Through 23-03-1996",

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TY - JOUR

T1 - FPGA-based high performance page layout segmentation

AU - Ratha, N. K.

AU - Jain, A. K.

AU - Rover, D. T.

PY - 1996

Y1 - 1996

N2 - A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2 - an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1.024 × 1.024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.

AB - A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2 - an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1.024 × 1.024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.

UR - https://www.scopus.com/pages/publications/0029720295

M3 - Conference article

AN - SCOPUS:0029720295

SN - 1066-1395

SP - 29

EP - 34

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI

Y2 - 22 March 1996 through 23 March 1996

ER -

FPGA-based high performance page layout segmentation

Abstract

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