TY - GEN
T1 - Fast Universal Decoder for Block Error Correcting Codes using Parallel Comparison
AU - Fritz, Christopher
AU - Fam, Adly T.
PY - 2013
Y1 - 2013
N2 - In this work, a fast decoder for Block Error Correcting Codes is introduced. It is based on comparing the received code word, with possible errors, to all codewords without errors in parallel. The Hamming distances between the received code word and all the correct code words are computed in parallel, and then each Hamming distance is compared to all the correctable values it can attain simultaneously. The code word with the smallest Hamming distance is chosen to be the correct code word. Any match for such a value blocks the output of all higher values. The result is a very fast circuit and method for decoding with propagation delay independent of the number of code words. Next to each code word, the data word that it encodes is stored and therefore either the corrected code word or the corresponding data word can be outputted. This parallel design allows for high throughput and short latency, rendering it particularly suited for applications such as error correcting RAM and communication channels. The decoder is programmable for any block error correcting code within its hardware capacity. Additionally, it works equally well for linear as well as nonlinear block error correcting codes and therefore represents a universal decoder.
AB - In this work, a fast decoder for Block Error Correcting Codes is introduced. It is based on comparing the received code word, with possible errors, to all codewords without errors in parallel. The Hamming distances between the received code word and all the correct code words are computed in parallel, and then each Hamming distance is compared to all the correctable values it can attain simultaneously. The code word with the smallest Hamming distance is chosen to be the correct code word. Any match for such a value blocks the output of all higher values. The result is a very fast circuit and method for decoding with propagation delay independent of the number of code words. Next to each code word, the data word that it encodes is stored and therefore either the corrected code word or the corresponding data word can be outputted. This parallel design allows for high throughput and short latency, rendering it particularly suited for applications such as error correcting RAM and communication channels. The decoder is programmable for any block error correcting code within its hardware capacity. Additionally, it works equally well for linear as well as nonlinear block error correcting codes and therefore represents a universal decoder.
KW - Communication Channels
KW - Cryptography
KW - Error correcting memory
KW - Fault tolerance
KW - Golay Codes
KW - Hadamard Codes
KW - Hamming Codes
KW - Hamming Distance
KW - Linear and Nonlinear Block Error Correcting Codes
UR - https://www.scopus.com/pages/publications/84891465707
U2 - 10.1109/MECO.2013.6601349
DO - 10.1109/MECO.2013.6601349
M3 - Conference contribution
AN - SCOPUS:84891465707
SN - 9789940943615
T3 - Proceedings - 2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013
SP - 176
EP - 179
BT - Proceedings - 2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013
T2 - 2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013
Y2 - 15 June 2013 through 20 June 2013
ER -