Skip to main navigation Skip to search Skip to main content

Enhanced Wallace Tree Multiplier via a Prefix Adder

  • SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

At the end of all fixed point multiplications is one last long addition that needs to be performed. In this paper, we show how the choice of this last adder has significant effect on the delay of the multiplier, in terms of time complexity. It is shown here that using a prefix adder for the final addition, causes the multiplication delay to increase as O(log[N]), as compared to the O(N) delay if a ripple carry adder is used instead. Simulations using spectre by Cadence, for 8,16,32, and 64 bit Wallace tree based multipliers, show that using a prefix adder instead of a ripple carry adder reduces the multiplier's latency by up to 66% at the cost of minimal increase in power consumption.

Original languageEnglish
Title of host publication2020 IEEE Student Conference on Research and Development, SCOReD 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages211-216
Number of pages6
ISBN (Electronic)9781728193175
DOIs
StatePublished - Sep 27 2020
Event2020 IEEE Student Conference on Research and Development, SCOReD 2020 - Virtual, Johor, Malaysia
Duration: Sep 27 2020Sep 28 2020

Publication series

Name2020 IEEE Student Conference on Research and Development, SCOReD 2020

Conference

Conference2020 IEEE Student Conference on Research and Development, SCOReD 2020
Country/TerritoryMalaysia
CityVirtual, Johor
Period09/27/2009/28/20

Keywords

  • Prefix Adder
  • Ripple Carry Adder
  • Time Complexity
  • Wallace Tree Multiplier

Fingerprint

Dive into the research topics of 'Enhanced Wallace Tree Multiplier via a Prefix Adder'. Together they form a unique fingerprint.

Cite this