Efficient decoupling capacitance budgeting considering operation and process variations

This paper solves the variation-aware on-chip decoupling capacitance (decap) budgeting problem. Unlike, previous work assuming the worst-case current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlation between clock cycles and logic-induced correlation between ports. The models also considers current variation due to process variation with spatial correlation. We then propose an iterative alternative programming algorithm to solve the decap budgeting problem under the stochastic current model. Experiments using industrial examples show that compared with the baseline model which assumes maximum currents at all ports and under the same, decap area constraint, the model considering temporal correlation reduces the noise by up to 5x, and the model considering both temporal and logic-induced correlations reduces the noise by up to 17x. Compared with the. model using deterministic process parameters, considering pmcess variation (L_eff variation in this paper) reduces the mean noise by up to 4x and the 3<r noise by up to 13 x. While the existing stochastic optimization has been used mainly for pmcess variation purpose, this paper to the best of our knowledge is the first in-depth study on stochastic optimization taking into account both operation and process variations for power network design. We convincingly show that considering operation variation is highly beneficial for power Integrity optimization and this should be researched for optimizing signal and thermal integrity as well.