Effect of process variation on the performance of phase frequency detector

Nandakumar P. Venugopal; Nihal Shastry; Shambhu J. Upadhyaya

doi:10.1109/DFT.2006.23

Effect of process variation on the performance of phase frequency detector

Nandakumar P. Venugopal
, Nihal Shastry
, Shambhu J. Upadhyaya

Department of Computer Science and Engineering

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS Phase Frequency Detector (PFD) is investigated. When a Phase Locked Loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence we consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was ldBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified.

Original language	English
Title of host publication	Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06
Pages	525-533
Number of pages	9
DOIs	https://doi.org/10.1109/DFT.2006.23
State	Published - 2006
Event	2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, United States Duration: Oct 4 2006 → Oct 6 2006

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Conference

Conference	2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Country/Territory	United States
City	Arlington, VA
Period	10/4/06 → 10/6/06

Keywords

Jitter
Monte Carlo simulation
NFET
PFET
Phase Frequency Detector (PFD)
Phase noise
Process variation

Access to Document

10.1109/DFT.2006.23

Cite this

Venugopal, N. P., Shastry, N., & Upadhyaya, S. J. (2006). Effect of process variation on the performance of phase frequency detector. In Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06 (pp. 525-533). Article 4030965 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2006.23

@inproceedings{63aec068998f4d84970211698f687dd2,

title = "Effect of process variation on the performance of phase frequency detector",

abstract = "In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS Phase Frequency Detector (PFD) is investigated. When a Phase Locked Loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence we consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was ldBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified.",

keywords = "Jitter, Monte Carlo simulation, NFET, PFET, Phase Frequency Detector (PFD), Phase noise, Process variation",

author = "Venugopal, \{Nandakumar P.\} and Nihal Shastry and Upadhyaya, \{Shambhu J.\}",

year = "2006",

doi = "10.1109/DFT.2006.23",

language = "English",

isbn = "076952706X",

series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

pages = "525--533",

booktitle = "Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06",

note = "2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ; Conference date: 04-10-2006 Through 06-10-2006",

}

Venugopal, NP, Shastry, N & Upadhyaya, SJ 2006, Effect of process variation on the performance of phase frequency detector. in Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06., 4030965, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 525-533, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Arlington, VA, United States, 10/4/06. https://doi.org/10.1109/DFT.2006.23

Effect of process variation on the performance of phase frequency detector. / Venugopal, Nandakumar P.; Shastry, Nihal; Upadhyaya, Shambhu J.
Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06. 2006. p. 525-533 4030965 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Effect of process variation on the performance of phase frequency detector

AU - Venugopal, Nandakumar P.

AU - Shastry, Nihal

AU - Upadhyaya, Shambhu J.

PY - 2006

Y1 - 2006

N2 - In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS Phase Frequency Detector (PFD) is investigated. When a Phase Locked Loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence we consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was ldBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified.

AB - In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS Phase Frequency Detector (PFD) is investigated. When a Phase Locked Loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence we consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was ldBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified.

KW - Jitter

KW - Monte Carlo simulation

KW - NFET

KW - PFET

KW - Phase Frequency Detector (PFD)

KW - Phase noise

KW - Process variation

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DO - 10.1109/DFT.2006.23

M3 - Conference contribution

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SN - 076952706X

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T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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BT - Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06

T2 - 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Y2 - 4 October 2006 through 6 October 2006

ER -

Effect of process variation on the performance of phase frequency detector

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Keywords

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