Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS

Shruti Konwar; Harshit Roy; Shiuh Hua Wood Chiang; Bibhu Datta Sahoo

doi:10.1109/LSSC.2022.3210768

Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS

Shruti Konwar
, Harshit Roy
, Shiuh Hua Wood Chiang
, Bibhu Datta Sahoo

Department of Electrical Engineering

Indian Institute of Technology Kharagpur
Alphabet Inc.
Brigham Young University

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

This letter presents a 12-bit binary-weighted successive approximation register (SAR) ADC calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch. A prototype 12-bit SAR ADC sampling at 8 MHz is realized in UMC 180-nm CMOS process and achieves an ENOB of 11.7-bits while consuming 600μ\W of power from 1.8-V supply, thereby achieving a figure-of-merit of 22.5 fJ/conv-s and occupying only 0.13 mm2.

Original language	English
Pages (from-to)	243-246
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	5
DOIs	https://doi.org/10.1109/LSSC.2022.3210768
State	Published - 2022

Keywords

Calibration
dithering
successive approximation register (SAR) ADC

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10.1109/LSSC.2022.3210768

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title = "Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS",

abstract = "This letter presents a 12-bit binary-weighted successive approximation register (SAR) ADC calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch. A prototype 12-bit SAR ADC sampling at 8 MHz is realized in UMC 180-nm CMOS process and achieves an ENOB of 11.7-bits while consuming 600μ\textbackslash{}W of power from 1.8-V supply, thereby achieving a figure-of-merit of 22.5 fJ/conv-s and occupying only 0.13 mm2.",

keywords = "Calibration, dithering, successive approximation register (SAR) ADC",

author = "Shruti Konwar and Harshit Roy and Chiang, \{Shiuh Hua Wood\} and Sahoo, \{Bibhu Datta\}",

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year = "2022",

doi = "10.1109/LSSC.2022.3210768",

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AU - Konwar, Shruti

AU - Roy, Harshit

AU - Chiang, Shiuh Hua Wood

AU - Sahoo, Bibhu Datta

PY - 2022

Y1 - 2022

N2 - This letter presents a 12-bit binary-weighted successive approximation register (SAR) ADC calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch. A prototype 12-bit SAR ADC sampling at 8 MHz is realized in UMC 180-nm CMOS process and achieves an ENOB of 11.7-bits while consuming 600μ\W of power from 1.8-V supply, thereby achieving a figure-of-merit of 22.5 fJ/conv-s and occupying only 0.13 mm2.

AB - This letter presents a 12-bit binary-weighted successive approximation register (SAR) ADC calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch. A prototype 12-bit SAR ADC sampling at 8 MHz is realized in UMC 180-nm CMOS process and achieves an ENOB of 11.7-bits while consuming 600μ\W of power from 1.8-V supply, thereby achieving a figure-of-merit of 22.5 fJ/conv-s and occupying only 0.13 mm2.

KW - Calibration

KW - dithering

KW - successive approximation register (SAR) ADC

UR - https://www.scopus.com/pages/publications/85139412926

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DO - 10.1109/LSSC.2022.3210768

M3 - Article

AN - SCOPUS:85139412926

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VL - 5

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JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

ER -

Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS

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Keywords

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