TY - GEN
T1 - Design for test perspective on memory synthesis
AU - Zarrineh, Kamran
AU - Upadhyaya, Shambhu J.
PY - 1999
Y1 - 1999
N2 - A novel approach based on a branch and bound technique is presented for transformation of logical memories to mappable physical memories while specified parameters such as area, delay, memory test time and test strategy are satisfied. The proposed algorithm uses the new test parameters to realize a logical memory with a set of physical memories which could be tested within the specified test time using the specified memory test strategy. The proposed framework generates and stores the realized logical memory in structural VHDL.
AB - A novel approach based on a branch and bound technique is presented for transformation of logical memories to mappable physical memories while specified parameters such as area, delay, memory test time and test strategy are satisfied. The proposed algorithm uses the new test parameters to realize a logical memory with a set of physical memories which could be tested within the specified test time using the specified memory test strategy. The proposed framework generates and stores the realized logical memory in structural VHDL.
UR - https://www.scopus.com/pages/publications/0032736825
M3 - Conference contribution
AN - SCOPUS:0032736825
SN - 0780354729
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - I-101 - I-104
BT - Proceedings - IEEE International Symposium on Circuits and Systems
PB - IEEE
T2 - Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
Y2 - 30 May 1999 through 2 June 1999
ER -